After the previous post about XNOR gate using 2:1 MUX, one might have thought that finally we exhausted the number of gates that we could make using 2:1 MUX. But that is not entirely true !!
There are still more devices that we can make using a 2:1 MUX. These are some of the favorite static timing analysis and logic design interview questions and they are about making memory elements using the 2:1 MUX.
We know the equation of a MUX is :
Out = S * A + (S)bar * B
We also know that level sensitive latch equation is
If ( Clock )
Q = D [ This means if Clock is high Q follows D ]
Q = Q [ If clock is off, Q holds previous state ]
We can rewrite this as following :
Q = Clock * D + (Clock)bar * Q
This means we can easily make a latch using 2:1 MUX like following.
Latch using a 2:1 MUX
When CLK is high it passes through D to O and when CLK is off, O is fed back to D0 input of mux, hence O appears back at the output, in other words, we retain the value of O when CLK is off. This is what exactly latch does.
So what else can we make now ?